The PM 3580/PM 3585 Logic analyzer family is a new 1 generation of general purpose logic analyzers giving twice the information with only half the work. All four models of this family {PM 3580/30, PM 3580/60, PM 3585/60, PM 3585/90) feature an exclusive Dual Analysis Per Pin architecture allowing these instruments to analyze and store state and timing data on each of up to 96 channels in a single acquisition at full speed, ail time correlated. No more dual probing; no more repeat measurements needed. The PM 3580 instruments handle 100 MHz timing and 50 MHz state acquisition on aii channeis simultaneously. The PM 3585 instruments handle 200 MHz timing and 50 MHz state acquisition on all channeis simultaneously. Operation of the instruments is more intuitive and easier than ever to learn. The modern human interface is user- friendly both in understanding and operation. Whenever you need them, popup menus will remind you of the choices available. So even if you do not use a logic analyzer very often, you will not be guessing. And when you know exactly where you want to be, you will find the short cuts even faster. For instance, you can type T to move the display directly to the trigger point. No menu needs to be involved. Simultaneous State and Timing Per Pin PM3585: Two Analyzers Both a timing section and a state section simultaneously observe the same target signals. The pattern recognition results (timing events and state events) of both sections are routed to one common sequencer. The sampled timing and state data are routed to the acquisition memory which can store a total of 2K samples (1K for PM 3580 units) and which you can assign to timing only data (100%), timing + glitch data (50%/50%), timing + state data (50%/50%), or state only data (100%). The pattern recognition logic for state and timing patterns operates independently from the storage mode you select. This allows you always to search for state and timing patterns in parallel. Inside your PM 3585 Logic Analyzer there are two independant Logic Analyzers, both having this unique Dual Analysis Per Pin architecture. These two analyzers can arm each other when and where necessary in their respective sequences. Channeis can be assigned in groups of 16 to either analyzer or remain unassigned. Both PM 3580 and PM 3585 units can use any channel as a state/externa! clock. Furthermore, any channel can be used as a clock qualifier. This is another unique feature of this iogic analyzer family. A maximum of 4 state clocks can be defined at the same time (per analyzer in PM 3585 units). Timing data is stored using the transitional timing mechanism. This guarantees an optimal usage of acquisition memory. The key features of ail four models are as follows: • “Dual Analysis Per Pin (DAPP)’’ architecture (simultaneous, correiated state and timing acquisition on all channeis) • Transitional timing on ail channels • Powerful triggering functionality integrating state & timing trigger functions in the same trigger sequence • Eight-ievei sequencer with full conditional structure (If...Then...Else) • Eight state trigger words • One range recognizer • Three timing trigger words • One edge detector • One glitch detector • Absolute or relative time stamp, always at full speed (5 ns resolution) • Powerful selective data acquisition functions.